Indicates whether the data to the transport layer is valid or invalid. The data format is big endian, where the earliest octet is placed in bit and the latest octet is placed in bit. Indicates a 32-bit data from the DLL to the transport layer. If byteenable is 4’b1111, uses 32-bit Dword Access otherwise uses byte access. Upper Ceiling(log2(L)) bits are lane select.īyte Enable. Only available when Transceiver Dynamic Reconfiguration option is enabled.Įach XCVR lanes address=18bits. Signal is synchronous with reconfig_xcvr_clk. The clock is recovered from the serial data stream. For PCS option in PMA Direct mode, this clock is half the frequency of rxlink_clk signal.ĭifferential high-speed serial input data.For PCS option in Hard PCS or Soft PCS mode, this clock has the same frequency as the rxlink_clk signal.This clock is derived from the clock data recovery (CDR) and the frequency depends on the F-Tile JESD204B IP core data rate. User must synchronize this signal before use.
User may optionally observe jesd204_rx_out_of_reset = 1 to indicate SIP out of reset to pulse SYSREF for subclass 1. (IP uses avs_clk or reconfig_xcvr_clk internally). To indicate the reset status of the SIP link layer. (IP use avs_clk or reconfig_xcvr_clk internally) To User to indicate that the IP is fully in reset. User is required to assert this reset if rx_avs_rst_n is asserted. Out of reset completion indicates by deassertion of rx_rst_ack_n. Reset sequence completion indicated by assertion rx_rst_ack_n.ĭeassertion triggers out-of-reset sequence. Async Assertion and Deassertion.Īssertion triggers reset sequence to MAC and PHY(Tile). To sample SYSREF correctly, the core PLL must provide the rxlink_clk signal and must be configured as normal operating mode.įrom User. This clock is equal to RX data rate divided by 40.įor Subclass 1, you cannot use the output of rxphy_clk signal as rxlink_clk signal. RX link clock signal used by the Avalon® streaming interface.
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